CS4364-CQZR【PDF 30/50 页】IC DAC 103DB 24BIT 6CH 48-LQFP

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Sheet目录1991

26页 27页 28页 29页 [30页]31页 32页 33页 34页

DS619F1

CS4364

6.4.2

Direct DSD Conversion (DIR_DSD)

Function:

When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-

tions.

When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.

In this mode, the full-scale DSD and PCM levels will not be matched (see Section 2), the dynamic range

performance may be reduced, the volume control is inactive, and the 50 kHz low-pass filter is not available

(see Section 2 for filter specifications).

6.4.3

Static DSD Detect (STATIC_DSD)

Function:

When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,

sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE

When set to 0, this function is disabled.

6.4.4

Invalid DSD Detect (INVALID_DSD)

Function:

When set to 1, the DSD processor checks for greater than 24 out of 28 bits of the same value and, if de-

tected, will attenuate the data sent to the DACs. The MUTEC pins go active according to the DAMUTE

When set to 0 (default), this function is disabled.

6.4.5

DSD Phase Modulation Mode Select (DSD_PM_MODE)

Function:

When set to 0 (default), the 128Fs (BCKA) clock should be input to DSD_SCLK for Phase Modulation

Mode. (See Figure 16 on page 24.)

When set to 1, the 64Fs (BCKD) clock should be input to DSD_SCLK for Phase Modulation Mode.

6.4.6

DSD Phase Modulation Mode Enable (DSD_PM_EN)

Function:

When set to 1, DSD Phase Modulation Input Mode is enabled and the DSD_PM_MODE bit should be set

accordingly.

When set to 0 (default), this function is disabled (DSD normal mode).

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